1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof. More particularly, the present invention relates to a semiconductor device solving problems arising in processing steps employing plasma and a manufacturing method thereof, and also relates to a highly controllable semiconductor device constituting pair transistors in an analog circuit or the like and a manufacturing method thereof.
2. Description of the Background Art
In course of manufacturing a large-scale integrated circuit (LSI), thin-film formation and etching thereof are repeated a number of times, for which various kinds of plasma processing utilizing plasma are employed.
In manufacture of a metal oxide semiconductor field effect transistor (MOSFET) or the like, a gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and using it as a mask, an impurity is ion implanted into the main surface of the semiconductor substrate. For example, phosphorus as the impurity is introduced into a p-type semiconductor substrate to form an n-type diffusion layer, which becomes source/drain regions. An interlayer insulating film and an interconnection layer are then formed thereon. A plurality of interlayer insulating films and interconnection layers are stacked alternately one on another.
In a process step utilizing such plasma processing, an interconnection layer electrically connected to the gate electrode collects charges from the plasma, so that a large voltage is applied between the gate insulating film and the semiconductor substrate. This phenomenon is referred to as the xe2x80x9cantenna effectxe2x80x9d. The antenna effect would not pose a serious problem with an LSI of low density.
With advancement of higher integration as seen in a dynamic random access memory (DRAM) or the like and promotion of downsizing of semiconductor devices, however, thinner gate insulating films and a greater number of interconnection layers have been employed. Consequently, the antenna effect has become prominent, and there are increased chances that the gate insulating films break due to charge up.
An antenna ratio as xe2x80x9carea of interconnection/area of channel regionxe2x80x9d or xe2x80x9cperipheral length of interconnection/peripheral length of channel regionxe2x80x9d, which is in proportion to the degree of charge up, has been regulated in an effort to restrict the charge up.
In addition, structures each having a protective diode connected to an interconnection layer have been proposed to prevent damages to the gate insulating films due to the antenna effect (Japanese Patent Laying-Open Nos. 2000-323582, 10-256393, 11-330467).
The formation of such a protective diode, however, makes mask and interconnection patterns more complicated, and the LSI manufacturing process more cumbersome. Further, some semiconductor devices have structures in which placement of such protective diodes is difficult. In addition, the protective diode thus placed may become a major stumbling block for downsizing of the semiconductor device.
In recent years, high-precision controllability of transistor characteristics has been required for an increasing number of circuits. FIG. 11 is a circuit diagram of a differential circuit including pair transistors commonly used in an analog circuit. In this differential circuit, two transistors 122a and 122b are required to have identical characteristics. Such matching or equality in characteristics of the pair transistors is impaired when their initial transistor characteristics like threshold voltages are different from each other due to different antenna ratios of interconnections connected to the two gates. As a result, variation in the threshold voltages or the like is amplified, resulting in variation in output voltage Vout of the differential circuit This causes defective circuits, and thus, the yield is degraded.
The above-described loss of matching characteristics of pair transistors is not solely attributable to the antenna effect. In addition to the countermeasures for the antenna effect, a variety of measures over the entire manufacturing process are required to ensure the matching characteristics of the pair transistors.
An object of the present invention is to provide a semiconductor device capable of restricting the antenna effect without an increase in complexity of the manufacturing process, and a manufacturing method thereof. Another object of the present invention is to provide a semiconductor device capable of readily ensuring matching in characteristics of pair transistors, and a manufacturing method thereof.
The semiconductor device according to an aspect of the present invention includes a plurality of transistors each having a gate electrode disposed on a semiconductor substrate on a gate insulating film. The semiconductor device includes: an interconnection that is arranged on an insulating film covering the gate electrode and the semiconductor substrate and is electrically connected to the gate electrode; a dummy transistor that is formed on the semiconductor substrate and is unprovided with an interconnection required for functioning as a transistor; and a connecting portion for electrically connecting the interconnection arranged on the insulating film to a source/drain region of the dummy transistor.
With such a structure, even if plasma is brought in contact with and introduced into the interconnection, the charges can escape via the source/drain region of the dummy transistor to the semiconductor substrate. This prevents accumulation of charges in the gate electrode, hindering application of a high voltage to the gate insulating film. As a result, the gate insulating film is prevented from suffering damage due to the antenna effect, so that initial transistor characteristics like threshold voltages can be maintained.
Even if the charges within the plasma are collected, not only during the aforementioned etching of the interconnection, but also during the formation of an insulating film thereon employing plasma, it is possible to make the charges escape via the source/drain region of the dummy transistor to the semiconductor substrate.
The dummy transistor is provided for dimensional control of the gate electrode. Non-uniformity in density of the gate pattern would affect photolithography and gate pattern etching, hindering an increase of dimensional accuracy. Thus, a dummy transistor is disposed to level the gate occupying ratio, and as a result, a gate pattern of uniform density is obtained.
The dummy transistor has its pattern formed in a mask pattern together with the pattern of a regular transistor, so that it is readily formed at the same time as the regular transistor. The source and drain regions of the dummy transistor are doped with impurities in the same concentrations as those of the regular transistor. Accordingly, compared to the case of providing a separate protective diode, provision of such a dummy transistor is simple in manufacture and advantageous to downsizing.
The semiconductor device according to another aspect of the present invention includes pairing transistors composed of a first transistor having a first gate electrode placed on a semiconductor substrate on a first gate insulating film and a second transistor having a second gate electrode placed on the semiconductor substrate on a second gate insulating film. The semiconductor device is provided with first and second interconnections placed on an insulating film covering the first and second gate electrodes and the semiconductor substrate. The first interconnection is electrically connected to the first gate electrode, and the second interconnection is electrically connected to the second gate electrode. The first and second interconnections have a structure ensuring equality or matching in characteristics of the first and second transistors.
The semiconductor device according to yet another aspect of the present invention includes pairing transistors composed of a first transistor having a first gate electrode placed on a semiconductor substrate on a first gate insulating film and a second transistor having a second gate electrode placed on the semiconductor substrate on a second gate insulating film, and also includes a dummy interconnection for averaging the effect of chemical mechanical polishing (CMP) that is provided in an upper layer than the first and second transistors. The dummy interconnection is arranged such that it does not overlap either of the pairing transistors in two dimensions, or such that a portion of the dummy interconnection overlapping the first transistor and a portion thereof overlapping the second transistor are equivalent to each other.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.